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| Features * Utilizes the AVR(R) RISC Architecture * AVR - High-performance and Low-power RISC Architecture - 118 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General-purpose Working Registers - Up to 10 MIPS Throughput at 10 MHz Data and Nonvolatile Program Memory - 2K Bytes of In-System Programmable Flash Endurance 1,000 Write/Erase Cycles - 128 Bytes of SRAM - 128 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles - Programming Lock for Flash Program and EEPROM Data Security Peripheral Features - One 8-bit Timer/Counter with Separate Prescaler - One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and 8-, 9- or 10-bit PWM - On-chip Analog Comparator - Programmable Watchdog Timer with On-chip Oscillator - SPI Serial Interface for In-System Programming - Full Duplex UART * Special Microcontroller Features - Low-power Idle and Power-down Modes - External and Internal Interrupt Sources * Specifications - Low-power, High-speed CMOS Process Technology - Fully Static Operation Power Consumption at 4 MHz, 3V, 25C - Active: 2.8 mA - Idle Mode: 0.8 mA - Power-down Mode: <1 A I/O and Packages - 15 Programmable I/O Lines - 20-pin PDIP and SOIC Operating Voltages - 2.7 - 6.0V (AT90S2313-4) - 4.0 - 6.0V (AT90S2313-10) Speed Grades - 0 - 4 MHz (AT90S2313-4) - 0 - 10 MHz (AT90S2313-10) * * * * * 8-bit Microcontroller with 2K Bytes of In-System Programmable Flash AT90S2313 * * * Pin Configuration PDIP/SOIC Rev. 0839G-08/01 1 Description The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. Figure 1. The AT90S2313 Block Diagram The AT90S2313 provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM, 128 bytes SRAM, 15 general-purpose I/O lines, 32 generalpurpose working registers, flexible timer/counters with compare modes, internal and external interrupts, a programmable serial UART, programmable Watchdog Timer with internal oscillator, an SPI serial port for Flash memory downloading and two software 2 AT90S2313 0839G-08/01 AT90S2313 selectable power-saving modes. The Idle Mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The Power-down Mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. The device is manufactured using Atmel's high-density nonvolatile memory technology. The on-chip In-System Programmable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S2313 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. The AT90S2313 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators and evaluation kits. Pin Descriptions VCC GND Port B (PB7..PB0) Supply voltage pin. Ground pin. Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip analog comparator. The Port B output buffers can sink 20 mA and can drive LED displays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current if the internal pullup resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not active. Port B also serves the functions of various special features of the AT90S2313 as listed on page 53. Port D (PD6..PD0) Port D has seven bi-directional I/O ports with internal pull-up resistors, PD6..PD0. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not active. Port D also serves the functions of various special features of the AT90S2313 as listed on page 58. RESET XTAL1 XTAL2 Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Output from the inverting oscillator amplifier. 3 0839G-08/01 Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 3. Figure 2. Oscillator Connections MAX 1 HC BUFFER HC C2 C1 XTAL2 XTAL1 GND Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure. Figure 3. External Clock Drive Configuration 4 AT90S2313 0839G-08/01 AT90S2313 Architectural Overview The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle. Figure 4. The AT90S2313 AVR RISC Architecture Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look-up function. These added function registers are the 16-bit X-register, Y-register and Z-register. The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4 shows the AT90S2313 AVR RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations. 5 0839G-08/01 The I/O memory space contains 64 addresses for CPU peripheral functions such as control registers, timer/counters, A/D converters and other I/O functions. The I/O memory can be accessed directly or as the Data Space locations following those of the register file, $20 - $5F. The AVR has Harvard architecture - with separate memories and buses for program and data. The program memory is accessed with a 2-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Programmable Flash memory. With the relative jump and call instructions, the whole 1K address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 8-bit stack pointer (SP) is read/write accessible in the I/O space. The 128 bytes data SRAM + register file and I/O registers can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. 6 AT90S2313 0839G-08/01 AT90S2313 Figure 5. Memory Maps A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. All the different interrupts have a separ a te i nt er r up t v e c to r i n t h e i n te r r u pt v ec t or t a bl e at th e b e gi n ni n g of th e program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. 7 0839G-08/01 General-purpose Register File Figure 6 shows the structure of the 32 general-purpose registers in the CPU. Figure 6. AVR CPU General-purpose Working Registers 7 R0 R1 R2 ... R13 General Purpose Working Registers R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 $1A $1B $1C $1D $1E $1F X-register low byte X-register high byte Y-register low byte Y-register high byte Z-register low byte Z-register high byte $0D $0E $0F $10 $11 0 Addr. $00 $01 $02 All the register operating instructions in the instruction set have direct and single-cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the register file (R16..R31). The general SBC, SUB, CP, AND, OR and all other operations between two registers or on a single register apply to the entire register file. As shown in Figure 6, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although the register file is not physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X, Y and Z registers can be set to index any register in the file. X-register, Y-register, and Zregister The registers R26..R31 have some added functions to their general-purpose usage. These registers are the address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined in Figure 7. Figure 7. X, Y and Z Registers 15 X-register 7 R27 ($1B) 0 7 R26 ($1A) 0 0 15 Y-register 7 R29 ($1D) 0 7 R28 ($1C) 0 0 15 Z-register 7 R31 ($1F) 0 7 R30 ($1E) 0 0 8 AT90S2313 0839G-08/01 AT90S2313 In the different addressing modes these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions). ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories - arithmetic, logical and bit functions. The AT90S2313 contains 2K bytes on-chip In-System Programmable Flash memory for program storage. Since all instructions are 16- or 32-bit words, the Flash is organized as 1K x 16. The Flash memory has an endurance of at least 1,000 write/erase cycles. The AT90S2313 Program Counter (PC) is 10 bits wide, thus addressing the 1,024 program memory addresses. See page 62 for a detailed description on Flash data downloading. See page 11 for the different addressing modes. In-System Programmable Flash Program Memory EEPROM Data Memory The AT90S2313 contains 128 bytes of EEPROM data memory. It is organized as a separate data space in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 40, specifying the EEPROM address register, the EEPROM data register and the EEPROM control register. For the SPI data downloading, see page 69 for a detailed description. 9 0839G-08/01 SRAM Data Memory Figure 8 shows how the AT90S2313 data memory is organized. Figure 8. SRAM Organization Register File R0 R1 R2 Data Address Space $00 $01 $02 ... R29 R30 R31 I/O Registers $00 $01 $02 ... $1D $1E $1F $20 $21 $22 ... $3D $3E $3F ... $5D $5E $5F Internal SRAM $60 $61 $62 ... $DD $DE $DF The 224 data memory locations address the Register file, I/O memory and the data SRAM. The first 96 locations address the Register File + I/O Memory, and the next 128 locations address the data SRAM. The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the register file, registers R26 to R31 feature the indirect addressing pointer registers. The Direct addressing reaches the entire data address space. The Indirect with Displacement mode features 63 address locations reached from the base address given by the Y and Z registers. When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y and Z are used and decremented and incremented. The 32 general-purpose working registers, 64 I/O registers and the 128 bytes of data SRAM in the AT90S2313 are all directly accessible through all these addressing modes. 10 AT90S2313 0839G-08/01 AT90S2313 Program and Data Addressing Modes The AT90S2313 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and data memory. This section describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. Figure 9. Direct Single Register Addressing Register Direct, Single Register Rd The operand is contained in register d (Rd). Register Direct, Two Registers Rd and Rr Figure 10. Direct Register Addressing, Two Registers Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 11. I/O Direct Addressing 11 0839G-08/01 Operand address is contained in 6 bits of the instruction word. n is the destination or source register address. Data Direct Figure 12. Direct Data Addressing A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify the destination or source register. Data Indirect with Displacement Figure 13. Data Indirect with Displacement Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction word. Data Indirect Figure 14. Data Indirect Addressing Operand address is the contents of the X-, Y- or Z-register. 12 AT90S2313 0839G-08/01 AT90S2313 Data Indirect with Predecrement Figure 15. Data Indirect Addressing with Pre-decrement The X-, Y- or Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y- or Z-register. Data Indirect with Postincrement Figure 16. Data Indirect Addressing with Post-increment The X-, Y- or Z-register is incremented after the operation. Operand address is the contents of the X-, Y- or Z-register prior to incrementing. Constant Addressing Using the LPM Instruction Figure 17. Code Memory Constant Addressing Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 1K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). 13 0839G-08/01 Indirect Program Addressing, IJMP and ICALL Figure 18. Indirect Program Memory Addressing Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). Relative Program Addressing, RJMP and RCALL Figure 19. Relative Program Memory Addressing Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047. Memory Access and Instruction Execution Timing This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock O, directly generated from the external clock crystal for the chip. No internal clock division is used. Figure 20 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks and functions per power-unit. 14 AT90S2313 0839G-08/01 AT90S2313 Figure 20. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 System Clock O 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 21 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 21. Single-cycle ALU Operation T1 T2 T3 T4 System Clock O Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back The internal data SRAM access is performed in two System Clock cycles as described in Figure 22. Figure 22. On-chip Data SRAM Access Cycles T1 T2 T3 T4 System Clock O Address Data WR Data RD Prev. Address Address 15 0839G-08/01 Read Write I/O Memory The I/O space definition of the AT90S2313 is shown in Table 1. Table 1. AT90S2313 I/O Space Address Hex $3F ($5F) $3D ($5D) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $35 ($55) $33 ($53) $32 ($52) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $25 ($45) $24 ($44) $21 ($41) $1E ($3E) $1D ($3D) $1C ($3C) $18 ($38) $17 ($37) $16 ($36) $12 ($32) $11 ($31) $10 ($30) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) Note: Name SREG SPL GIMSK GIFR TIMSK TIFR MCUCR TCCR0 TCNT0 TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL ICR1H ICR1L WDTCR EEAR EEDR EECR PORTB DDRB PINB PORTD DDRD PIND UDR USR UCR UBRR ACSR Function Status Register Stack Pointer Low General Interrupt MaSK register General Interrupt Flag Register Timer/Counter Interrupt MaSK register Timer/Counter Interrupt Flag register MCU general Control Register Timer/Counter 0 Control Register Timer/Counter 0 (8-bit) Timer/Counter 1 Control Register A Timer/Counter 1 Control Register B Timer/Counter 1 High Byte Timer/Counter 1 Low Byte Output Compare Register 1 High Byte Output Compare Register 1 Low Byte T/C 1 Input Capture Register High Byte T/C 1 Input Capture Register Low Byte Watchdog Timer Control Register EEPROM Address Register EEPROM Data Register EEPROM Control Register Data Register, Port B Data Direction Register, Port B Input Pins, Port B Data Register, Port D Data Direction Register, Port D Input Pins, Port D UART I/O Data Register UART Status Register UART Control Register UART Baud Rate Register Analog Comparator Control and Status Register Reserved and unused locations are not shown in the table. All AT90S2313 I/O and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general-pur- 16 AT90S2313 0839G-08/01 AT90S2313 pose working registers and the I/O space. I/O registers within the address range $00 $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as SRAM, $20 must be added to this address. All I/O register addresses throughout this document are shown with the SRAM address in parentheses. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the status flags are cleared by writing a logical "1" to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a "1" back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. The I/O and peripherals control registers are explained in the following sections. Status Register - SREG The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as: Bit $3F ($5F) Read/Write Initial value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG * Bit 7 - I: Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. * Bit 6 - T: Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. * Bit 5 - H: Half-carry Flag The half-carry flag H indicates a half-carry in some arithmetic operations. See the Instruction Set description for detailed information. * Bit 4 - S: Sign Bit, S = N V The S-bit is always an exclusive or between the negative flag N and the two's complement overflow flag V. See the Instruction Set description for detailed information. * Bit 3 - V: Two's Complement Overflow Flag The two's complement overflow flag V supports two's complement arithmetics. See the Instruction Set description for detailed information. * Bit 2 - N: Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set description for detailed information. * Bit 1 - Z: Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set description for detailed information. 17 0839G-08/01 * Bit 0 - C: Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set description for detailed information. Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. Stack Pointer - SP An 8-bit register at I/O address $3D ($5D) forms the stack pointer of the AT90S2313. 8 bits are used to address the 128 bytes of SRAM in locations $60 - $DF. Bit $3D ($5D) Read/Write Initial value 7 SP7 R/W 0 6 SP6 R/W 0 5 SP5 R/W 0 4 SP4 R/W 0 3 SP3 R/W 0 2 SP2 R/W 0 1 SP1 R/W 0 0 SP0 R/W 0 SPL The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt stacks are located. This stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above $60. The Stack Pointer is decremented by 1 when data is pushed onto the stack with the PUSH instruction, and it is decremented by 2 when an address is pushed onto the stack with subroutine calls and interrupts. The Stack Pointer is incremented by 1 when data is popped from the stack with the POP instruction, and it is incremented by 2 when an address is popped from the stack with return from subroutine RET or return from interrupt RETI. Reset and Interrupt Handling The AT90S2313 provides 10 different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits that must be set (one) together with the I-bit in the Status Register in order to enable the interrupt. The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The complete list of vectors is shown in Table 2. The list also determines the priority levels of the different interrupts. The lower the address, the higher the priority level. RESET has the highest priority, and next is INT0 (the External Interrupt Request 0), etc. Table 2. Reset and Interrupt Vectors Vector No. 1 2 3 4 5 6 7 8 Program Address $000 $001 $002 $003 $004 $005 $006 $007 Source RESET INT0 INT1 TIMER1 CAPT1 TIMER1 COMP1 TIMER1 OVF1 TIMER0 OVF0 UART, RX Interrupt Definition Hardware Pin, Power-on Reset and Watchdog Reset External Interrupt Request 0 External Interrupt Request 1 Timer/Counter1 Capture Event Timer/Counter1 Compare Match Timer/Counter1 Overflow Timer/Counter0 Overflow UART, RX Complete 18 AT90S2313 0839G-08/01 AT90S2313 Table 2. Reset and Interrupt Vectors (Continued) Vector No. 9 10 11 Program Address $008 $009 $00A Source UART, UDRE UART, TX ANA_COMP Interrupt Definition UART Data Register Empty UART, TX Complete Analog Comparator The most typical and general program setup for the Reset and Interrupt vector addresses are: Address Labels Code Comments $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a ; $00b $00c $00d ... MAIN: rjmp RESET rjmp EXT_INT0 rjmp EXT_INT1 rjmp TIM_CAPT1 rjmp TIM_COMP1 rjmp TIM_OVF1 rjmp TIM_OVF0 rjmp UART_RXC rjmp UART_DRE rjmp UART_TXC rjmp ANA_COMP ; Reset Handler ; IRQ0 Handler ; IRQ1 Handler ; Timer1 Capture Handler ; Timer1 Compare Handler ; Timer1 Overflow Handler ; Timer0 Overflow Handler ; UART RX Complete Handler ; UDR Empty Handler ; UART TX Complete Handler ; Analog Comparator Handler ldi r16,low(RAMEND); Main program start out SPL,r16 ... Reset Sources The AT90S2313 has three sources of reset: * * * Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns. Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled. During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000. The instruction placed in address $000 must be an RJMP (relative jump) instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 23 shows the reset logic. Table 3 defines the timing and electrical parameters of the reset circuitry. 19 0839G-08/01 Figure 23. Reset Logic Table 3. Reset Characteristics (VCC = 5.0V) Symbol VPOT(1) VRST tTOUT tTOUT Note: Parameter Power-on Reset Threshold Voltage (rising) Power-on Reset Threshold Voltage (falling) RESET Pin Threshold Voltage Reset Delay Time-out Period FSTRT Unprogrammed Reset Delay Time-out Period FSTRT Programmed 11.0 0.25 Min 1.0 0.4 Typ 1.4 0.6 - 16.0 0.28 Max 1.8 0.8 0.85 VCC 21.0 0.31 Units V V V ms ms 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling). The user can select the start-up time according to typical oscillator start-up. The number of WDT oscillator cycles used for each time-out is shown in Table 4. The frequency of the Watchdog Oscillator is voltage-dependent, as shown in "Typical Characteristics" on page 75. Table 4. Number of Watchdog Oscillator Cycles FSTRT Programmed Unprogrammed Time-out at VCC = 5V 0.28 ms 16.0 ms Number of WDT Cycles 256 16K Power-on Reset A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As shown in Figure 23, an internal timer is clocked from the Watchdog Timer. This timer prevents the MCU from starting until after a certain period after VCC has reached the Power-on Threshold voltage (VPOT) (see Figure 24). The FSTRT Fuse bit in the Flash can be programmed to give a shorter start-up time if a ceramic resonator or any other fast-start oscillator is used to clock the MCU. If the built-in start-up delay is sufficient, RESET can be connected to VCC directly or via an external pull-up resistor. By holding the RESET pin low for a period after VCC has been applied, the Power-on Reset period can be extended. Refer to Figure 25 for a timing example of this. 20 AT90S2313 0839G-08/01 AT90S2313 Figure 24. MCU Start-up, RESET Tied to VCC. VCC VPOT RESET VRST TIME-OUT tTOUT INTERNAL RESET Figure 25. MCU Start-up, RESET Controlled Externally VCC VPOT RESET VRST TIME-OUT tTOUT INTERNAL RESET External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage (VRST) on its positive edge, the delay timer starts the MCU after the Time-out period tTOUT has expired. Figure 26. External Reset during Operation 21 0839G-08/01 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one XTAL cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 38 for details on operation of the Watchdog. Figure 27. Watchdog Reset during Operation Interrupt Handling The AT90S2313 has two 8-bit Interrupt Mask control registers: the GIMSK (General Interrupt Mask register) and the TIMSK (Timer/Counter Interrupt Mask register). When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable interrupts. The Ibit is set (one) when a Return from Interrupt instruction (RETI) is executed. For interrupts triggered by events that can remain static (e.g., the Output Compare Register1 matching the value of Timer/Counter1), the interrupt flag is set when the event occurs. If the interrupt flag is cleared and the interrupt condition persists, the flag will not be set until the event occurs the next time. When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a logical "1" to the flag bit position(s) to be cleared. If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority. Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is active. Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. 22 AT90S2313 0839G-08/01 AT90S2313 General Interrupt Mask Register - GIMSK Bit $3B ($5B) Read/Write Initial value 7 INT1 R/W 0 6 INT0 R/W 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIMSK * Bit 7 - INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also "External Interrupts". * Bit 6 - INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also "External Interrupts." * Bits 5..0 - Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read as zero. General Interrupt FLAG Register - GIFR Bit $3A ($5A) Read/Write Initial value 7 INTF1 R/W 0 6 INTF0 R/W 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIFR * Bit 7 - INTF1: External Interrupt Flag1 When an edge on the INT1 pin triggers an interrupt request, the corresponding interrupt flag, INTF1, becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT1 bit in GIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical "1" to it. The flag is always cleared when INT1 is configured as level interrupt. * Bit 6 - INTF0: External Interrupt Flag0 When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt flag, INTF0, becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT0 bit in GIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical "1" to it. The flag is always cleared when INT0 is configured as level interrupt. * Bits 5..0 - Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read as zero. Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is active. 23 0839G-08/01 Timer/Counter Interrupt Mask Register - TIMSK Bit $39 ($59) Read/Write Initial value 7 TOIE1 R/W 0 6 OCIE1A R/W 0 5 - R 0 4 - R 0 3 TICIE1 R/W 0 2 - R 0 1 TOIE0 R/W 0 0 - R 0 TIMSK * Bit 7 - TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding interrupt (at vector $005) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]). * Bit 6 - OCIE1A: Timer/Counter1 Output Compare Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare Match Interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a compare match in Timer/Counter1 occurs (i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register [TIFR]). * Bit 5,4 - Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read as zero. * Bit 3 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on PD6(ICP) (i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]). * Bit 2 - Res: Reserved Bit This bit is a reserved bit in the AT90S2313 and always reads as zero. * Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter0 occurs (i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]). * Bit 0 - Res: Reserved Bit This bit is a reserved bit in the AT90S2313 and always read as zero. Timer/Counter Interrupt FLAG Register - TIFR Bit $38 ($58) Read/Write Initial value 7 TOV1 R/W 0 6 OCF1A R/W 0 5 - R 0 4 - R 0 3 ICF1 R/W 0 2 - R 0 1 TOV0 R/W 0 0 - R 0 TIFR * Bit 7 - TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logical "1" to the flag. When the I-bit in SREG and TOIE1 (T i mer /Counter 1 O v erfl ow Inte rr upt Enabl e) and TOV 1 ar e s et ( one ), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000. * Bit 6 - OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when a compare match occurs between the Timer/Counter1 and the data in OCR1A (Output Compare Register1 A). OCF1A is cleared by hardware 24 AT90S2313 0839G-08/01 AT90S2313 when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logical "1" to the flag. When the I-bit in SREG and OCIE1A (Timer/Counter1 Compare Match Interrupt Enable) and the OCF1A are set (one), the Timer/Counter1 Compare Match Interrupt is executed. * Bits 5, 4 - Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read as zero. * Bit 3 - ICF1: Input Capture Flag 1 The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logical "1" to the flag. When the SREG I-bit and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. * Bit 2 - Res: Reserved Bit This bit is a reserved bit in the AT90S2313 and always reads as zero. * Bit 1 - TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical "1" to the flag. When the SREG I-bit and TOIE0 (T i mer /Counter 0 O v erfl ow Inte rr upt Enabl e) and TOV 0 ar e s et ( one ), the Timer/Counter0 Overflow Interrupt is executed. * Bit 0 - Res: Reserved Bit This bit is a reserved bit in the AT90S2313 and always reads as zero. External Interrupts The External Interrupts are triggered by the INT1 and INT0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register (MCUCR). When the External Interrupt is enabled and is configured as level-triggered, the interrupt will trigger as long as the pin is held low. The External Interrupts are set up as described in the specification for the MCU Control Register (MCUCR). Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles, minimum. Four clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this 4-clock-cycle period, the Program Counter (2 bytes) is pushed onto the stack, and the Stack Pointer is decremented by 2. The vector is normally a relative jump to the interrupt routine, and this jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is popped back from the stack, the Stack Pointer is incremented by 2, and the I-flag in SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. 25 0839G-08/01 MCU Control Register - MCUCR The MCU Control Register contains control bits for general MCU functions. Bit $35 ($55) Read/Write Initial value 7 - R 0 6 - R 0 5 SE R/W 0 4 SM R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR * Bits 7, 6 - Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read as zero. * Bit 5 - SE: Sleep Enable The SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEP instruction is executed. To avoid the MCU entering the Sleep Mode unless it is the programmer's purpose, it is recommended to set the Sleep Enable (SE) bit just before the execution of the SLEEP instruction. * Bit 4 - SM: Sleep Mode This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode. When SM is set (one), Power-down Mode is selected as Sleep Mode. For details, refer to the paragraph "Sleep Modes". * Bits 3, 2 - ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the GIMSK register is set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 5. Table 5. Interrupt 1 Sense Control ISC11 0 0 1 1 ISC10 0 1 0 1 Description The low level of INT1 generates an interrupt request. Reserved The falling edge of INT1 generates an interrupt request. The rising edge of INT1 generates an interrupt request. * Bits 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask is set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 6. Table 6. Interrupt 0 Sense Control ISC01 0 0 1 1 ISC00 0 1 0 1 Description The low level of INT0 generates an interrupt request. Reserved The falling edge of INT0 generates an interrupt request. The rising edge of INT0 generates an interrupt request. The value on the INTn pin is sampled before detecting edges. If edge interrupt is selected, pulses with a duration longer than one CPU clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate an interrupt request as long as the pin is held low. 26 AT90S2313 0839G-08/01 AT90S2313 Sleep Modes To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file, SRAM and I/O memory are unaltered. If a reset occurs during Sleep Mode, the MCU wakes up and executes from the Reset vector. When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle Mode, stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external triggered interrupts as well as internal ones like Timer Overflow interrupt and Watchdog reset. If wake-up from the Analog Comparator Interrupt is not required, the Analog Comparator can be powered down by setting the ACD-bit in the Analog Comparator Control and Status Register (ACSR). This will reduce power consumption in Idle Mode. When the MCU wakes up from Idle Mode, the CPU starts program execution immediately. When the SM bit is set (one), the SLEEP instruction forces the MCU into the Powerdown Mode. In this mode, the external oscillator is stopped while the external interrupts and the Watchdog (if enabled) continue operating. Only an external reset, a Watchdog reset (if enabled), an external level interrupt on INT0 or INT1 can wake up the MCU. Note that when a level-triggered interrupt is used for wake-up from power-down, the low level must be held for a time longer than the reset delay Time-out period tTOUT. Otherwise, the device will not wake up. Idle Mode Power-down Mode Timer/Counters The AT90S2313 provides two general-purpose Timer/Counters - one 8-bit T/C and one 16-bit T/C. The Timer/Counters have individual prescaling selection from the same 10bit prescaling timer. Both Timer/Counters can either be used as a timer with an internal clock time base or as a counter with an external pin connection that triggers the counting. 27 0839G-08/01 Timer/Counter Prescaler Figure 28 shows the general Timer/Counter prescaler. Figure 28. Timer/Counter Prescaler TCK1 TCK0 The four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024, where CK is the oscillator clock. For the two Timer/Counters, added selections such as CK, external clock source and stop can be selected as clock sources. 8-bit Timer/Counter0 Figure 29 shows the block diagram for Timer/Counter0. The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an external pin. In addition, it can be stopped as described in the specification for the Timer/Counter0 Control Register (TCCR0). The overflow status flag is found in the Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the Timer/Counter0 Control Register (TCCR0). The interrupt enable/disable settings for Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register (TIMSK). When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high-resolution and a high-accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions. 28 AT90S2313 0839G-08/01 AT90S2313 Figure 29. Timer/Counter0 Block Diagram T0 Timer/Counter0 Control Register - TCCR0 Bit $33 ($53) Read/Write Initial value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 CS02 R/W 0 1 CS01 R/W 0 0 CS00 R/W 0 TCCR0 * Bits 7..3 - Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read zero. * Bits 2,1,0 - CS02, CS01, CS00: Clock Select0, Bit 2,1 and 0 The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0. Table 7. Clock 0 Prescale Select CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 Description Stop, the Timer/Counter0 is stopped. CK CK/8 CK/64 CK/256 CK/1024 External Pin T0, falling edge External Pin T0, rising edge 29 0839G-08/01 The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on PD4/(T0) will clock the counter even if the pin is configured as an output. This feature can give the user software control of the counting. Timer/Counter0 - TCNT0 Bit $32 ($52) Read/Write Initial value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 TCNT0 The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the timer clock cycle following the write operation. 16-bit Timer/Counter1 Figure 30 shows the block diagram for Timer/Counter1. Figure 30. Timer/Counter1 Block Diagram 6 The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK or an external pin. In addition, it can be stopped as described in the specification for the Timer/Counter1 Control Register (TCCR1B). The different status flags (Overflow, Compare Match and Capture Event) and control signals are found in the Timer/Counter Interrupt Flag Register (TIFR). The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register (TIMSK). 30 AT90S2313 0839G-08/01 AT90S2313 When Timer/Counter1 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 16-bit Timer/Counter1 features both a high-resolution and a high-accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities makes the Timer/Counter1 useful for lower speed functions or exact timing functions with infrequent actions. The Timer/Counter1 supports an Output Compare function using the Output Compare Register 1A (OCR1A) as the data source to be compared to the Timer/Counter1 contents. The Output Compare functions include optional clearing of the counter on compare matches, and actions on the Output Compare pin 1 on compare matches. Timer/Counter1 can also be used as an 8-, 9- or 10-bit Pulse Width Modulator. In this mode the counter and the OCR1 register serve as a glitch-free standalone PWM with centered pulses. Refer to page 36 for a detailed description of this function. The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1 contents to the Input Capture Register (ICR1), triggered by an external event on the Input Capture Pin (ICP). The actual capture event settings are defined by the Timer/Counter1 Control Register (TCCR1B). In addition, the Analog Comparator can be set to trigger the input capture. Refer to "Analog Comparator" on page 50 for details on this. The ICP pin logic is shown in Figure 31. Figure 31. ICP Pin Schematic Diagram If the Noise Canceler function is enabled, the actual trigger condition for the capture event is monitored over four samples, and all four must be equal to activate the capture flag. Timer/Counter1 Control Register A - TCCR1A Bit $2F ($4F) Read/Write Initial value 7 COM1A1 6 COM1A0 5 - 4 - 3 - 2 - 1 PWM11 0 PWM10 TCCR1A R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 * Bits 7,6 - COM1A1, COM1A0: Compare Output Mode1, Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1 (Output Compare pin 1) (PB3). This is an alternative function to the I/O port, and the corresponding 31 0839G-08/01 direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 8. Table 8. Compare 1 Mode Select COM1A1 0 0 1 1 Note: COM1A0 0 1 0 1 Description Timer/Counter1 disconnected from output pin OC1 Toggle the OC1 output line. Clear the OC1 output line (to zero). Set the OC1 output line (to one). In PWM mode, these bits have a different function. Refer to Table 12 for a detailed description. * Bits 5..2 - Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read zero. * Bits 1,0 - PWM11, PWM10: Pulse Width Modulator Select Bits These bits select PWM operation of Timer/Counter1 as specified in Table 9. This mode is described on page 35. Table 9. PWM Mode Select PWM11 0 0 1 1 PWM10 0 1 0 1 Description PWM operation of Timer/Counter1 is disabled Timer/Counter1 is an 8-bit PWM Timer/Counter1 is a 9-bit PWM Timer/Counter1 is a 10-bit PWM Timer/Counter1 Control Register B - TCCR1B Bit $2E ($4E) Read/Write Initial value 7 ICNC1 R/W 0 6 ICES1 R/W 0 5 - R 0 4 - R 0 3 CTC1 R/W 0 2 CS12 R/W 0 1 CS11 R/W 0 0 CS10 R/W 0 TCCR1B * Bit 7 - ICNC1: Input Capture1 Noise Canceler (4 CKs) When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP (input capture pin) as specified. When the ICNC1 bit is set (one), four successive samples are measured on the ICP (input capture pin), and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is the XTAL clock frequency. * Bit 6 - ICES1: Input Capture1 Edge Select While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register (ICR1) on the falling edge of the input capture pin (ICP). While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register (ICR1) on the rising edge of the input capture pin (ICP). * Bits 5, 4 - Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read zero. 32 AT90S2313 0839G-08/01 AT90S2313 * Bit 3 - CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. Since the compare match is detected in the CPU clock cycle following the match, this function will behave differently when a prescaling higher than 1 is used for the timer. When a prescaling of 1 is used, and the compareA register is set to C, the timer will count as follows if CTC1 is set: ... | C-2 | C-1 | C | 0 | 1 |... When the prescaler is set to divide by 8, the timer will count like this: ... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0, 0, 0, 0, 0, 0, 0 |... In PWM mode, this bit has no effect. * Bits 2,1,0 - CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0 The Clock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1. Table 10. Clock 1 Prescale Select CS12 0 0 0 0 1 1 1 1 CS11 0 0 1 1 0 0 1 1 CS10 0 1 0 1 0 1 0 1 Description Stop, the Timer/Counter1 is stopped. CK CK/8 CK/64 CK/256 CK/1024 External Pin T1, falling edge External Pin T1, rising edge The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter1, transitions on PD5/(T1) will clock the counter even if the pin is configured as an output. This feature can give the user software control of the counting. Timer/Counter1 - TCNT1H and TCNT1L Bit $2D ($4D) $2C ($4C) 15 MSB 14 13 12 11 10 9 8 TCNT1H LSB TCNT1L 7 Read/Write Initial value R/W R/W 0 0 6 R/W R/W 0 0 5 R/W R/W 0 0 4 R/W R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 0 R/W R/W 0 0 This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A and ICR1. If the main program and interrupt routines perform access to registers using TEMP, inter- 33 0839G-08/01 rupts must be disabled during access from the main program or interrupts if interrupts are re-enabled. * TCNT1 Timer/Counter1 Write: When the CPU writes to the high byte TCNT1H, the written data is placed in the TEMP register. Next, when the CPU writes the low byte TCNT1L, this byte of data is combined with the byte data in the TEMP register, and all 16 bits are written to the TCNT1 Timer/Counter1 register simultaneously. Consequently, the high byte TCNT1H must be accessed first for a full 16-bit register write operation. TCNT1 Timer/Counter1 Read: When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent to the CPU and the data of the high byte TCNT1H is placed in the TEMP register. When the CPU reads the data in the high byte TCNT1H, the CPU receives the data in the TEMP register. Consequently, the low byte TCNT1L must be accessed first for a full 16-bit register read operation. * The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value. Timer/Counter1 Output Compare Register A - OCR1AH and OCR1AL Bit $2B ($4B) $2A ($4A) 15 MSB 14 13 12 11 10 9 8 OCR1AH LSB OCR1AL 7 Read/Write Initial value R/W R/W 0 0 6 R/W R/W 0 0 5 R/W R/W 0 0 4 R/W R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 0 R/W R/W 0 0 The output compare register is a 16-bit read/write register. The Timer/Counter1 Output Compare Register contains the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status registers. Since the Output Compare Register (OCR1A) is a 16-bit register, a temporary register TEMP is used when OCR1A is written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL, the TEMP register is simultaneously written to OCR1AH. Consequently, the high byte OCR1AH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program or interrupts if interrupts are re-enabled. 34 AT90S2313 0839G-08/01 AT90S2313 Timer/Counter1 Input Capture Register - ICR1H and ICR1L Bit $25 ($45) $24 ($44) 15 MSB 14 13 12 11 10 9 8 ICR1H LSB ICR1L 7 Read/Write Initial value R R 0 0 6 R R 0 0 5 R R 0 0 4 R R 0 0 3 R R 0 0 2 R R 0 0 1 R R 0 0 0 R R 0 0 The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting [ICES1]) of the signal at the input capture pin (ICP) is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register (ICR1). At the same time, the input capture flag (ICF1) is set (one). Since the Input Capture Register (ICR1) is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1 and OCR1A. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program or interrupts if interrupts are re-enabled. Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1 (OCR1A) form an 8-, 9- or 10-bit, free-running, glitch-free and phase-correct PWM with output on the PB3(OC1) pin. Timer/Counter1 acts as an up/down counter, counting up from $0000 to TOP (see Table 11), where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the contents of the 8, 9 or 10 least significant bits of OCR1A, the PB3(OC1) pin is set or cleared according to the settings of the COM1A1 and COM1A0 bits in the Timer/Counter1 Control Register (TCCR1). Refer to Table 12 for details. Table 11. Timer TOP Values and PWM Frequency PWM Resolution 8-bit 9-bit 10-bit Timer TOP Value $00FF (255) $01FF (511) $03FF(1023) Frequency fTC1/510 fTC1/1022 fTC1/2046 35 0839G-08/01 Table 12. Compare1 Mode Select in PWM Mode COM1A1 0 0 1 1 COM1A0 0 1 0 1 Effect on OC1 Not connected Not connected Cleared on compare match, upcounting. Set on compare match, down-counting (non-inverted PWM). Cleared on compare match, downcounting. Set on compare match, up-counting (inverted PWM). Note that in the PWM mode, the 10 least significant OCR1A bits, when written, are transferred to a temporary location. They are latched when Timer/Counter1 reaches TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A write. See Figure 32 for an example. Figure 32. Effects on Unsynchronized OCR1 Latching Compare Value changes Compare Value changes During the time between the write and the latch operations, a read from OCR1A will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A. When the OCR1 contains $0000 or TOP, the output OC1 is updated to low or high on the next compare match according to the settings of COM1A1/COM1A0. This is shown in Table 13. Note: If the compare register contains the TOP value and the prescaler is not in use (CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the upcounting and down-counting values are reached simultaneously. When the prescaler is in use (CS12..CS10 001 or 000), the PWM output goes active when the counter reaches the TOP value, but the down-counting compare match is not interpreted to be reached before the next time the counter reaches the TOP value, making a one-period PWM pulse. 36 AT90S2313 0839G-08/01 AT90S2313 Table 13. PWM Outputs OCR = $0000 or TOP COM1A1 1 1 1 1 COM1A0 0 0 1 1 OCR1A $0000 TOP $0000 TOP Output OC1 L H H L In PWM mode, the Timer Overflow Flag1 (TOV1) is set when the counter advances from $0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode (i.e., it is executed when TOV1 is set, provided that Timer Overflow Interrupt1 and global interrupts are enabled). This also applies to the Timer Output Compare1 flag and interrupt. 37 0839G-08/01 Watchdog Timer The Watchdog Timer is clocked from a separate on-chip oscillator that runs at 1 MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted. See Table 14 for a detailed description. The WDR (Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog reset, the AT90S2313 resets and executes from the reset vector. For timing details on the Watchdog reset, refer to page 22. To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer Control Register for details. Figure 33. Watchdog Timer Watchdog Timer Control Register - WDTCR Bit $21 ($41) Read/Write Initial value 7 - R 0 6 - R 0 5 - R 0 4 WDTOE R/W 0 3 WDE R/W 0 2 WDP2 R/W 0 1 WDP1 R/W 0 0 WDP0 R/W 0 WDTCR * Bits 7..5 - Res: Reserved Bits These bits are reserved bits in the AT90S2313 and will always read as zero. * Bit 4 - WDTOE: Watchdog Turn-off Enable This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. * Bit 3 - WDE: Watchdog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero), the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logical "1" to WDTOE and WDE. A logical "1" must be written to WDE even though it is set to 1 before the disable operation starts. 2. Within the next four clock cycles, write a logical "0" to WDE. This disables the Watchdog. 38 AT90S2313 0839G-08/01 AT90S2313 * Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0 The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in Table 14. Table 14. Watchdog Timer Prescale Select Number of WDT Oscillator Cycles 16K cycles 32K cycles 64K cycles 128K cycles 256K cycles 512K cycles 1,024K cycles 2,048K cycles Typical Time-out at VCC = 3.0V 47 ms 94 ms 0.19 s 0.38 s 0.75 s 1.5 s 3.0 s 6.0 s Typical Time-out at VCC = 5.0V 15 ms 30 ms 60 ms 0.12 s 0,24 s 0.49 s 0.97 s 1.9 s WDP2 0 0 0 0 1 1 1 1 Note: WDP1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 The frequency of the Watchdog Oscillator is voltage-dependent, as shown in the Electrical Characteristics section. The WDR (Watchdog Reset) instruction should always be executed before the Watchdog Timer is enabled. This ensures that the reset period will be in accordance with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the Watchdog Timer may not start counting from zero. To avoid unintentional MCU reset, the Watchdog Timer should be disabled or reset before changing the Watchdog Timer Prescale Select. 39 0839G-08/01 EEPROM Read/Write Access The EEPROM access registers are accessible in the I/O space. The write access time is in the range of 2.5 - 4 ms, depending on the VCC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some precaution must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on powerup/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions may cause the Program Counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. EEPROM Address Register - EEAR Bit $1E ($3E) Read/Write Initial value 7 - R 0 6 EEAR6 R/W 0 5 EEAR5 R/W 0 4 EEAR4 R/W 0 3 EEAR3 R/W 0 2 EEAR2 R/W 0 1 EEAR1 R/W 0 0 EEAR0 R/W 0 EEAR * Bit 7 - Res: Reserved Bit This bit is a reserved bit in the AT90S2313 and will always read as zero. * Bit 6..0 - EEAR6..0: EEPROM Address The EEPROM Address Register (EEAR6..0) specifies the EEPROM address in the 128 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127. EEPROM Data Register - EEDR Bit $1D ($3D) Read/Write Initial value 7 MSB R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 LSB R/W 0 EEDR * Bit 7..0 - EEDR7..0: EEPROM Data For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. EEPROM Control Register - EECR Bit $1C ($3C) Read/Write Initial value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 EEMWE R/W 0 1 EEWE R/W 0 0 EERE R/W 0 EECR * Bit 7..3 - Res: Reserved Bits These bits are reserved bits in the AT90S2313 and will always read as zero. 40 AT90S2313 0839G-08/01 AT90S2313 * Bit 2 - EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure. * Bit 1 - EEWE: EEPROM Write Enable The EEPROM Write Enable Signal (EEWE) is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical "1" is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEAR (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical "1" to the EEMWE bit in EECR (to be able to write a logical "1" to the EEMWE bit, the EEWE bit must be written to zero in the same cycle). 5. Within four clock cycles after setting EEMWE, write a logical "1" to EEWE. When the write access time (typically 2.5 ms at VCC = 5V or 4 ms at VCC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the last four steps to avoid these problems. * Bit 0 - EERE: EEPROM Read Enable The EEPROM Read Enable Signal (EERE) is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted and the result is undefined. Prevent EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board-level systems using the EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly if the supply voltage for executing instructions is too low. EEPROM data corruption can easily be avoided by following these design recommendations (one is sufficient): 41 0839G-08/01 1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This is best done by an external low VCC Reset Protection circuit, often referred to as a Brown-out Detector (BOD). Please refer to the AVR 180 application note for design considerations regarding power-on reset and low-voltage detection. 2. Keep the AVR core in Power-down Sleep Mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the EEPROM registers from unintentional writes. 3. Store constants in Flash memory if the ability to change memory contents from software is not required. Flash memory cannot be updated by the CPU and will not be subject to corruption. 42 AT90S2313 0839G-08/01 AT90S2313 UART The AT90S2313 features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are: * Baud Rate Generator that can Generate a Large Number of Baud Rates (bps) * High Baud Rates at Low XTAL Frequencies * 8 or 9 Bits Data * Noise Filtering * Overrun Detection * Framing Error Detection * False Start Bit Detection * Three separate Interrupts on TX Complete, TX Data Register Empty and RX Complete A block schematic of the UART transmitter is shown in Figure 34. Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register (UDR). Data is transferred from UDR to the Transmit shift register when: * * A new character has been written to UDR after the stop bit from the previous character has been shifted out. The shift register is loaded immediately. A new character has been written to UDR before the stop bit from the previous character has been shifted out. The shift register is loaded when the stop bit of the character currently being transmitted has been shifted out. Data Transmission Figure 34. UART Transmitter If the 10(11)-bit Transmitter shift register is empty, data is transferred from UDR to the shift register. At this time the UDRE (UART Data Register Empty) bit in the UART Status 43 0839G-08/01 Register (USR) is set. When this bit is set (one), the UART is ready to receive the next character. At the same time as the data is transferred from UDR to the 10(11)-bit shift register, bit 0 of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9bit data word is selected (the CHR9 bit in the UART Control Register [UCR] is set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit shift register. On the Baud Rate clock following the transfer operation to the shift register, the start bit is shifted out on the TXD pin. Then follows the data, LSB first. When the stop bit has been shifted out, the shift register is loaded if any new data has been written to the UDR during the transmission. During loading, UDRE is set. If there is no new data in the UDR register to send when the stop bit is shifted out, the UDRE flag will remain set until UDR is written again. When no new data has been written, and the stop bit has been present on TXD for one bit length, the TX Complete Flag (TXC) in USR is set. The TXEN bit in UCR enables the UART transmitter when set (one). When this bit is cleared (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART Transmitter will be connected to PD1, which is forced to be an output pin regardless of the setting of the DDD1 bit in DDRD. Data Reception Figure 35 shows a block diagram of the UART Receiver. Figure 35. UART Receiver 44 AT90S2313 0839G-08/01 AT90S2313 The receiver front-end logic samples the signal on the RXD pin at a frequency of 16 times the baud rate. While the line is idle, one single sample of logical "0" will be interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample. Following the 1-to-0 transition, the receiver samples the RXD pin at samples 8, 9 and 10. If two or more of these three samples are found to be logical "1"s, the start bit is rejected as a noise spike and the receiver starts looking for the next 1-to-0 transition. If, however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also sampled at samples 8, 9 and 10. The logical value found in at least two of the three samples is taken as the bit value. All bits are shifted into the transmitter shift register as they are sampled. Sampling of an incoming character is shown in Figure 36. Figure 36. Sampling Received Data When the stop bit enters the receiver, the majority of the three samples must be "1" to accept the stop bit. If two or more samples are logical "0"s, the Framing Error (FE) flag in the UART Status Register (USR) is set. Before reading the UDR register, the user should always check the FE bit to detect Framing Errors. Whether or not a valid stop bit is detected at the end of a character-reception cycle, the data is transferred to UDR and the RXC flag in USR is set. UDR is in fact two physically separate registers; one for transmitted data and one for received data. When UDR is read, the Receive Data register is accessed, and when UDR is written, the Transmit Data register is accessed. If 9-bit data word is selected (the CHR9 bit in the UART Control Register [UCR] is set), the RXB8 bit in UCR is loaded with bit 9 in the Transmit shift register when data is transferred to UDR. If, after having received a character, the UDR register has not been read since the last receive, the OverRun (OR) flag in UCR is set. This means that the last data byte shifted into the shift register could not be transferred to UDR and has been lost. The OR bit is buffered and is updated when the valid data byte in UDR is read. Thus, the user should always check the OR bit after reading the UDR register in order to detect any overruns if the baud rate is high or CPU load is high. When the RXEN bit in the UCR register is cleared (zero), the receiver is disabled. This means that the PD0 pin can be used as a general I/O pin. When RXEN is set, the UART Receiver will be connected to PD0, which is forced to be an input pin regardless of the setting of the DDD0 bit in DDRD. When PD0 is forced to input by the UART, the PORTD0 bit can still be used to control the pull-up resistor on the pin. When the CHR9 bit in the UCR register is set, transmitted and received characters are nine bits long plus start and stop bits. The ninth data bit to be transmitted is the TXB8 bit in UCR register. This bit must be set to the wanted value before a transmission is initiated by writing to the UDR register. The ninth data bit received is the RXB8 bit in the UCR register. 45 0839G-08/01 UART Control The UART I/O Data Register - UDR Bit $0C ($2C) Read/Write Initial value 7 MSB R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 LSB R/W 0 UDR The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. When reading from UDR, the UART Receive Data register is read. UART Status Register - USR Bit $0B ($2B) Read/Write Initial value 7 RXC R 0 6 TXC R/W 0 5 UDRE R 1 4 FE R 0 3 OR R 0 2 - R 0 1 - R 0 0 - R 0 USR The USR register is a read-only register providing information on the UART status. * Bit 7 - RXC: UART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is set (one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates. * Bit 6 - TXC: UART Transmit Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical "1" to the bit. * Bit 5 - UDRE: UART Data Register Empty This bit is set (one) when a character written to UDR is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt is executed as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates. UDRE is set (one) during reset to indicate that the transmitter is ready. * Bit 4 - FE: Framing Error This bit is set if a Framing Error condition is detected (i.e., when the stop bit of an incoming character is zero). 46 AT90S2313 0839G-08/01 AT90S2313 The FE bit is cleared when the stop bit of received data is one. * Bit 3 - OR: Overrun This bit is set if an Overrun condition is detected (i.e., when a character already present in the UDR register is not read before the next character has been shifted into the Receiver Shift register). The OR bit is buffered, which means that it will be set once the valid data still in UDRE is read. The OR bit is cleared (zero) when data is received and transferred to UDR. * Bits 2..0 - Res: Reserved Bits These bits are reserved bits in the AT90S2313 and will always read as zero. UART Control Register - UCR Bit $0A ($2A) Read/Write Initial value 7 RXCIE R/W 0 6 TXCIE R/W 0 5 UDRIE R/W 0 4 RXEN R/W 0 3 TXEN R/W 0 2 CHR9 R/W 0 1 RXB8 R 1 0 TXB8 W 0 UCR * Bit 7 - RXCIE: RX Complete Interrupt Enable When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete Interrupt routine to be executed provided that global interrupts are enabled. * Bit 6 - TXCIE: TX Complete Interrupt Enable When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete Interrupt routine to be executed provided that global interrupts are enabled. * Bit 5 - UDRIE: UART Data Register Empty Interrupt Enable When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register Empty Interrupt routine to be executed provided that global interrupts are enabled. * Bit 4 - RXEN: Receiver Enable This bit enables the UART receiver when set (one). When the receiver is disabled, the RXC, OR and FE status flags cannot become set. If these flags are set, turning off RXEN does not cause them to be cleared. * Bit 3 - TXEN: Transmitter Enable This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the transmitter is not disabled before the character in the shift register plus any following character in UDR has been completely transmitted. * Bit 2 - CHR9: 9 Bit Characters When this bit is set (one), transmitted and received characters are nine bits long plus start and stop bits. The ninth bit is read and written by using the RXB8 and TXB8 bits in UCR, respectively. The ninth data bit can be used as an extra stop bit or a parity bit. * Bit 1 - RXB8: Receive Data Bit 8 When CHR9 is set (one), RXB8 is the ninth data bit of the received character. * Bit 0 - TXB8: Transmit Data Bit 8 When CHR9 is set (one), TXB8 is the ninth data bit in the character to be transmitted. 47 0839G-08/01 Baud Rate Generator The baud rate generator is a frequency divider that generates baud rates according to the following equation: f CK BAUD = -----------------------------------16(UBRR + 1) * * * BAUD = Baud Rate fCK = Crystal Clock frequency UBRR = Contents of the UART Baud Rate register (UBRR) (0 - 255) For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBRR settings in Table 15. UBRR values that yield an actual baud rate differing less than 2% from the target baud rate, are boldfaced in the table. However, using baud rates that have more than 1% error is not recommended. High error ratings give less noise resistance. 48 AT90S2313 0839G-08/01 AT90S2313 Table 15. UBRR Settings at Various Crystal Frequencies Baud Rate 1 MHz %Error 1.8432 MHz %Error 2 MHz %Error 2.4576 MHz %Error 2400 UBRR= 25 0.2 UBRR= 47 0.0 UBRR= 51 0.2 UBRR= 63 0.0 4800 UBRR= 12 0.2 UBRR= 23 0.0 UBRR= 25 0.2 UBRR= 31 0.0 6 7.5 UBRR= 9600 UBRR= 11 0.0 UBRR= 12 0.2 UBRR= 15 0.0 3 7.8 UBRR= 8 3.7 UBRR= 10 3.1 14400 UBRR= 7 0.0 UBRR= 2 7.8 UBRR= 6 7.5 UBRR= 19200 UBRR= 5 0.0 UBRR= 7 0.0 1 7.8 UBRR= 3 7.8 UBRR= 4 6.3 28800 UBRR= 3 0.0 UBRR= 1 22.9 UBRR= 2 7.8 UBRR= 38400 UBRR= 2 0.0 UBRR= 3 0.0 0 7.8 UBRR= 1 7.8 UBRR= 2 12.5 57600 UBRR= 1 0.0 UBRR= 0 22.9 UBRR= 1 33.3 UBRR= 1 22.9 UBRR= 76800 UBRR= 1 0.0 0 84.3 UBRR= 0 7.8 UBRR= 0 25.0 115200 UBRR= 0 0.0 UBRR= Baud Rate 3.2768 MHz %Error 3.6864 MHz %Error 4 MHz %Error 4.608 MHz %Error 2400 UBRR= 84 0.4 UBRR= 95 0.0 UBRR= 103 0.2 UBRR= 119 0.0 4800 UBRR= 42 0.8 UBRR= 47 0.0 UBRR= 51 0.2 UBRR= 59 0.0 9600 UBRR= 20 1.6 UBRR= 23 0.0 UBRR= 25 0.2 UBRR= 29 0.0 16 2.1 UBRR= 14400 UBRR= 13 1.6 UBRR= 15 0.0 UBRR= 19 0.0 10 3.1 UBRR= 19200 UBRR= 11 0.0 UBRR= 12 0.2 UBRR= 14 0.0 8 3.7 UBRR= 28800 UBRR= 6 1.6 UBRR= 7 0.0 UBRR= 9 0.0 4 6.3 UBRR= 6 7.5 UBRR= 7 6.7 38400 UBRR= 5 0.0 UBRR= 3 12.5 UBRR= 3 7.8 UBRR= 57600 UBRR= 3 0.0 UBRR= 4 0.0 2 12.5 UBRR= 2 7.8 UBRR= 3 6.7 76800 UBRR= 2 0.0 UBRR= 1 12.5 UBRR= 1 7.8 UBRR= 2 20.0 115200 UBRR= 1 0.0 UBRR= Baud Rate 7.3728 MHz %Error 8 MHz %Error 9.216 MHz %Error 11.059 MHz %Error 2400 UBRR= 191 0.0 UBRR= 207 0.2 UBRR= 239 0.0 UBRR= 287 4800 UBRR= 95 0.0 UBRR= 103 0.2 UBRR= 119 0.0 UBRR= 143 0.0 9600 UBRR= 47 0.0 UBRR= 51 0.2 UBRR= 59 0.0 UBRR= 71 0.0 14400 UBRR= 31 0.0 UBRR= 34 0.8 UBRR= 39 0.0 UBRR= 47 0.0 19200 UBRR= 23 0.0 UBRR= 25 0.2 UBRR= 29 0.0 UBRR= 35 0.0 16 2.1 UBRR= 28800 UBRR= 15 0.0 UBRR= 19 0.0 UBRR= 23 0.0 38400 UBRR= 11 0.0 UBRR= 12 0.2 UBRR= 14 0.0 UBRR= 17 0.0 8 3.7 UBRR= 57600 UBRR= 7 0.0 UBRR= 9 0.0 UBRR= 11 0.0 6 7.5 UBRR= 7 6.7 UBRR= 76800 UBRR= 5 0.0 UBRR= 8 0.0 3 7.8 UBRR= 115200 UBRR= 3 0.0 UBRR= 4 0.0 UBRR= 5 0.0 UART Baud Rate Register - UBRR Bit $09 ($29) Read/Write Initial value 7 MSB R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 LSB R/W 0 UBRR The UBRR register is an 8-bit read/write register that specifies the UART Baud Rate according to the formula on the previous page. 49 0839G-08/01 Analog Comparator The Analog Comparator compares the input values on the positive input AIN0 (PB0) and the negative input PB1(AIN1). When the voltage on the positive input PB0 (AIN0) is higher than the voltage on the negative input PB1 (AIN1), the Analog Comparator Output, ACO is set (one). The comparator's output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt exclusive to the Analog Comparator. The user can select interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 37. Figure 37. Analog Comparator Block Diagram Analog Comparator Control and Status Register - ACSR Bit $08 ($28) Read/Write Initial value 7 ACD R/W 0 6 - R 0 5 ACO R N/A 4 ACI R/W 0 3 ACIE R/W 0 2 ACIC R/W 0 1 ACIS1 R/W 0 0 ACIS0 R/W 0 ACSR * Bit 7 - ACD: Analog Comparator Disable When this bit is set (one), the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in active and idle modes. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. * Bit 6 - Res: Reserved Bit This bit is a reserved bit in the AT90S2313 and will always read as zero. * Bit 5 - ACO: Analog Comparator Output ACO is directly connected to the comparator output. * Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logical "1" to the flag. Observe, however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be cleared if it has become set before the operation. 50 AT90S2313 0839G-08/01 AT90S2313 * Bit 3 - ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Analog Comparator interrupt is activated. When cleared (zero), the interrupt is disabled. * Bit 2 - ACIC: Analog Comparator Input Capture Enable When set (one), this bit enables the Input Capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is, in this case, directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge-select features of the Timer/Counter1 Input Capture interrupt. When cleared (zero), no connection between the Analog Comparator and the Input Capture function is given. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one). * Bits 1,0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events trigger the Analog Comparator interrupt. The different settings are shown in Table 16. Table 16. ACIS1/ACIS0 Settings ACIS1 0 0 1 1 Note: ACIS0 0 1 0 1 Interrupt Mode Comparator Interrupt on Output Toggle Reserved Comparator Interrupt on Falling Output Edge Comparator Interrupt on Rising Output Edge When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR register. Otherwise an interrupt can occur when the bits are changed. 51 0839G-08/01 I/O Ports All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Port B is an 8-bit bi-directional I/O port. Three I/O memory address locations are allocated for the Port B, one each for the Data Register - PORTB, $18 ($38), Data Direction Register - DDRB, $17($37) and the Port B Input Pins - PINB, $16($36). The Port B Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pull-up resistors. The Port B output buffers can sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port B pins with alternate functions are shown in Table 17. Table 17. Port B Pin Alternate Functions Port Pin PB0 PB1 PB3 PB5 PB6 PB7 Alternate Functions AIN0 (Analog comparator positive input) AIN1 (Analog comparator negative input) OC1 (Timer/Counter1 Output compare match output) MOSI (Data input line for memory downloading) MISO (Data output line for memory uploading) SCK (Serial clock input) Port B When the pins are used for the alternate function, the DDRB and PORTB registers have to be set according to the alternate function description. Port B Data Register - PORTB Bit $18 ($38) Read/Write Initial value 7 PORTB7 6 PORTB6 5 PORTB5 4 PORTB4 3 PORTB3 2 PORTB2 1 PORTB1 0 PORTB0 PORTB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Port B Data Direction Register - DDRB Bit $17 ($37) Read/Write Initial value 7 DDB7 R/W 0 6 DDB6 R/W 0 5 DDB5 R/W 0 4 DDB4 R/W 0 3 DDB3 R/W 0 2 DDB2 R/W 0 1 DDB1 R/W 0 0 DDB0 R/W 0 DDRB Port B Input Pins Address - PINB Bit $16 ($36) Read/Write Initial value 7 PINB7 R N/A 6 PINB6 R N/A 5 PINB5 R N/A 4 PINB4 R N/A 3 PINB3 R N/A 2 PINB2 R N/A 1 PINB1 R N/A 0 PINB0 R N/A PINB 52 AT90S2313 0839G-08/01 AT90S2313 The Port B Input Pins address (PINB) is not a register; this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. Port B as General Digital I/O All eight pins in Port B have equal functionality when used as digital I/O pins. PBn, general I/O pin: The DDBn bit in the DDRB register selects the direction of this pin. If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) when the pin is configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the PORTBn has to be cleared (zero) or the pin has to be configured as an output pin The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not active. Table 18. DDBn Effects on Port B Pins DDBn 0 0 1 1 Note: PORTBn 0 1 0 1 I/O Input Input Output Output Pull-up No Yes No No Comment Tri-state (High-Z) PBn will source current if ext. pulled low Push-pull Zero Output Push-pull One Output n: 7,6...0, pin number. Alternate Functions of Port B The alternate pin functions of Port B are: * SCK - Port B, Bit 7 SCK, Clock input pin for memory up/downloading. * MISO - Port B, Bit 6 MISO, Data output pin for memory uploading. * MOSI - Port B, Bit 5 MOSI, Data input pin for memory downloading. * OC1 - Port B, Bit 3 OC1, Output Compare Match Output. The PB3 pin can serve as an external output for timer 1 compare match. The PB3 pin has to be configured as an output (DDB3 is set [one]) to serve this function. See the timer description for further details, and how to enable the output. * AIN1 - Port B, Bit 1 AIN1, Analog Comparator Negative Input. When configured as an input (DDB1 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB1 is cleared [zero]), this pin also serves as the negative input of the on-chip Analog Comparator. * AIN0 - Port B, Bit 0 AIN0, Analog Comparator Positive Input. When configured as an input (DDB0 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB0 is cleared [zero]), this pin also serves as the positive input of the on-chip Analog Comparator. 53 0839G-08/01 Port B Schematics Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 38. Port B Schematic Diagram (Pins PB0 and PB1) 54 AT90S2313 0839G-08/01 AT90S2313 Figure 39. Port B Schematic Diagram (Pin PB3) RD MOS PULLUP RESET R DDB3 C Q D WD RESET R Q D PORTB3 C RL DATA BUS COM1A0 COM1A1 OUTPUT MODE SELECT COMP. MATCH1 PB3 WP RP WP: WD: RL: RP: RD: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB Figure 40. Port B Schematic Diagram (Pins PB2 and PB4) 55 0839G-08/01 Figure 41. Port B Schematic Diagram (Pin PB5) Figure 42. Port B Schematic Diagram (Pin PB6) 56 AT90S2313 0839G-08/01 AT90S2313 Figure 43. Port B Schematic Diagram (Pin PB7) Port D Three I/O memory address locations are allocated for the Port D: one each for the Data Register - PORTD, $12($32), Data Direction Register - DDRD, $11($31) and the Port D Input Pins - PIND, $10($30). The Port D Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. Port D has seven bi-directional I/O pins with internal pull-up resistors, PD6..PD0. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Some Port D pins have alternate functions as shown in Table 19: Table 19. Port D Pin Alternate Functions Port Pin PD0 PD1 PD2 PD3 PD4 PD5 PD6 Alternate Function RXD (Receive data input for the UART) TXD (Transmit data output for the UART) INT0 (External interrupt 0 input) INT1 (External interrupt 1 input) TO (Timer/Counter0 external input) T1 (Timer/Counter1 external input) ICP (Timer/Counter1Input Capture pin) When the pins are used for the alternate function, the DDRD and PORTD registers have to be set according to the alternate function description. 57 0839G-08/01 Port D Data Register - PORTD Bit $12 ($32) Read/Write Initial value 7 - 6 PORTD6 5 PORTD5 4 PORTD4 3 PORTD3 2 PORTD2 1 PORTD1 0 PORTD0 PORTD R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Port D Data Direction Register - DDRD Bit $11 ($31) Read/Write Initial value 7 - R 0 6 DDD6 R/W 0 5 DDD5 R/W 0 4 DDD4 R/W 0 3 DDD3 R/W 0 2 DDD2 R/W 0 1 DDD1 R/W 0 0 DDD0 R/W 0 DDRD Port D Input Pins Address - PIND Bit $10 ($30) Read/Write Initial value 7 - R 0 6 PIND6 R N/A 5 PIND5 R N/A 4 PIND4 R N/A 3 PIND3 R N/A 2 PIND2 R N/A 1 PIND1 R N/A 0 PIND0 R N/A PIND The Port D Input Pins address (PIND) is not a register; this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read. Port D as General Digital I/O PDn, general I/O pin: The DDDn bit in the DDRD register selects the direction of this pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PORTDn is set (one) when configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the PORTDn has to be cleared (zero) or the pin has to be configured as an output pin. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not active. Table 20. DDDn Bits on Port D Pins DDDn 0 0 1 1 Note: PORTDn 0 1 0 1 I/O Input Input Output Output Pull-up No Yes No No Comment Tri-state (High-Z) PDn will source current if ext. pulled low Push-pull Zero Output Push-pull One Output n: 6...0, pin number. Alternate Functions of Port D The alternate functions of Port D are: * ICP - Port D, Bit 6 Timer/Counter1 Input Capture pin. See the Timer/Counter1 description for further details. * T1 - Port D, Bit 5 T1, Timer 1 clock source. See the Timer description for further details. * T0 - Port D, Bit 4 T0, Timer/Counter0 clock source. See the Timer description for further details. * INT1 - Port D, Bit 3 INT1, External Interrupt Source 1. The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source. 58 AT90S2313 0839G-08/01 AT90S2313 * INT0 - Port D, Bit 2 INT0, External Interrupt Source 0. The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source. * TXD - Port D, Bit 1 Transmit Data (Data output pin for the UART). When the UART transmitter is enabled, this pin is configured as an output regardless of the value of DDRD1. * RXD - Port D, Bit 0 Receive Data (Data input pin for the UART). When the UART receiver is enabled, this pin is configured as an input regardless of the value of DDRD0. When the UART forces this pin to be an input, a logical "1" in PORTD0 will turn on the internal pull-up. Port D Schematics Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 44. Port D Schematic Diagram (Pin PD0) RD MOS PULLUP RESET Q D DDD0 C RESET PD0 Q D PORTD0 C RL WP RP WP: WD: RL: RP: RD: RXD: RXEN: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD UART RECEIVE DATA UART RECEIVE ENABLE RXEN RXD DATA BUS WD 59 0839G-08/01 Figure 45. Port D Schematic Diagram (Pin PD1) RD MOS PULLUP RESET R Q D DDD1 C RESET R Q D PORTD1 C RL PD1 WP RP WP: WD: RL: RP: RD: TXD: TXEN: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD UART TRANSMIT DATA UART TRANSMIT ENABLE TXEN TXD Figure 46. Port D Schematic Diagram (Pins PD2 and PD3) 60 AT90S2313 0839G-08/01 DATA BUS WD AT90S2313 Figure 47. Port D Schematic Diagram (Pins PD4 and PD5) RD MOS PULLUP RESET R Q D DDDn C RESET R Q D PORTDn C RL PDn WP RP WP: WD: RL: RP: RD: n: m: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD 4, 5 0, 1 SENSE CONTROL TIMERm CLOCK SOURCE MUX CSm2 CSm1 CSm0 Figure 48. Port D Schematic Diagram (Pin PD6) DATA BUS WD 61 0839G-08/01 Memory Programming Program and Data Memory Lock Bits The AT90S2313 MCU provides two Lock bits that can be left unprogrammed ("1") or can be programmed ("0") to obtain the additional features listed in Table 21. The Lock bits can only be erased with the Chip Erase operation. Table 21. Lock Bit Protection Modes Memory Lock Bits Mode 1 2 3 Note: LB1 1 0 0 LB2 1 1 0 Protection Type No memory lock features enabled. Further programming of the Flash and EEPROM is disabled.(1) Same as mode 2, and verify is also disabled. 1. In the Parallel mode, further programming of the Fuse bits are also disabled. Program the Fuse bits before programming the Lock bits. Fuse Bits The AT90S2313 has two Fuse bits: SPIEN and FSTRT. * * When the SPIEN Fuse is programmed ("0"), Serial Program and Data Downloading is enabled. The default value is programmed ("0"). When the FSTRT Fuse is programmed ("0"), the short start-up time is selected. The default value is unprogrammed ("1"). Parts with this bit pre-programmed ("0") can be delivered on demand. The Fuse bits are not accessible in Serial Programming Mode. The status of the Fuses are not affected by Chip Erase. Signature Bytes All Atmel microcontrollers have a 3-byte signature code that identifies the device. This code can be read in both serial and parallel mode. The three bytes reside in a separate address space. For the AT90S2313(1) they are: 1. $000: $1E (indicates manufactured by Atmel) 2. $001: $91 (indicates 2 Kb Flash memory) 3. $002: $01 (indicates AT90S2313 device when signature byte $001 is $91) Note: 1. When both Lock bits are programmed (Lock mode 3), the signature bytes cannot be read in serial mode. Reading the signature bytes will return: $00, $01 and $02. Programming the Flash and EEPROM Atmel's AT90S2313 offers 2K bytes of in-system reprogrammable Flash program memory and 128 bytes of EEPROM data memory. The AT90S2313 is shipped with the on-chip Flash program and EEPROM data memory arrays in the erased state (i.e., contents = $FF) and ready to be programmed. This device supports a high-voltage (12V) Parallel Programming Mode and a low-voltage Serial Programming Mode. The +12V is used for programming enable only, and no current of significance is drawn by this pin. The Serial Programming Mode provides a convenient way to download program and data into the AT90S2313 inside the user's system. The program and EEPROM memory arrays in the AT90S2313 are programmed byteby-byte in either programming mode. For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction in the Serial Programming Mode. During programming, the supply voltage must be in accordance with Table 22. 62 AT90S2313 0839G-08/01 AT90S2313 Table 22. Supply Voltage during Programming Part AT90S2313 Serial Programming 2.7 - 6.0V Parallel Programming 4.5 - 5.5V Parallel Programming Signal Names This section describes how to parallel program and verify Flash program memory, EEPROM data memory, Lock bits and Fuse bits in the AT90S2313. In this section, some pins of the AT90S2313 are referenced by signal names describing their function during parallel programming. Pins not described in the following table are referenced by pin names. See Figure 49 and Table 23. Pins not described in Table 23 are referenced by pin names. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 24. When pulsing WR or OE, the command loaded determines the action executed. The command is a byte where the different bits are assigned functions as shown in Table 25. Figure 49. Parallel Programming . Table 23. Pin Name Mapping Signal Name in Programming Mode RDY/BSY OE WR BS XA0 XA1 DATA Pin Name PD1 PD2 PD3 PD4 PD5 PD6 PB7-0 I/O O I I I I I I/O Function 0: Device is busy programming, 1: Device is ready for new command Output Enable (Active low) Write Pulse (Active low) Byte Select ("0" selects low byte, "1" selects high byte) XTAL Action Bit 0 XTAL Action Bit 1 Bi-directional Data Bus (Output when OE is low) 63 0839G-08/01 Table 24. XA1 and XA0 Coding XA1 0 0 1 1 XA0 0 1 0 1 Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS) Load Data (High or Low data byte for Flash determined by BS) Load Command No Action, Idle Table 25. Command Byte Bit Coding Command Byte 1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011 Command Executed Chip Erase Write Fuse Bits Write Lock Bits Write Flash Write EEPROM Read Signature Bytes Read Fuse and Lock Bits Read Flash Read EEPROM Enter Programming Mode The following algorithm puts the device in Parallel Programming Mode: 1. Apply supply voltage according to Table 22, between VCC and GND. 2. Set the RESET and BS pin to "0" and wait at least 100 ns. 3. Apply 11.5 - 12.5V to RESET. Any activity on BS within 100 ns after +12V has been applied to RESET, will cause the device to fail entering Programming Mode. Chip Erase The Chip Erase command will erase the Flash and EEPROM memories, and the Lock bits. The Lock bits are not reset until the Flash and EEPROM have been completely erased. The Fuse bits are not changed. Chip Erase must be performed before the Flash or EEPROM is reprogrammed. Load Command "Chip Erase" 1. Set XA1, XA0 to "10". This enables command loading. 2. Set BS to "0". 3. Set DATA to "1000 0000". This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a tWLWH_CE wide negative pulse to execute Chip Erase. See Table 26 for tWLWH_CE value. Chip Erase does not generate any activity on the RDY/BSY pin. Programming the Flash A: Load Command "Write Flash" 1. Set XA1, XA0 to "10". This enables command loading. 2. Set BS to "0". 3. Set DATA to "0001 0000". This is the command for Write Flash. 64 AT90S2313 0839G-08/01 AT90S2313 4. Give XTAL1 a positive pulse. This loads the command. B: Load Address High Byte 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS to "1". This selects high byte. 3. Set DATA = Address high byte ($00 - $03). 4. Give XTAL1 a positive pulse. This loads the address high byte. C: Load Address Low Byte 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS to "0". This selects low byte. 3. Set DATA = Address low byte ($00 - $FF). 4. Give XTAL1 a positive pulse. This loads the address low byte. D: Load Data Low Byte 1. Set XA1, XA0 to "01". This enables data loading. 2. Set DATA = Data low byte ($00 - $FF). 3. Give XTAL1 a positive pulse. This loads the data low byte. E: Write Data Low Byte 1. Set BS to "0". This selects low data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. (See Figure 50 for signal waveforms.) F: Load Data High Byte 1. Set XA1, XA0 to "01". This enables data loading. 2. Set DATA = Data high byte ($00 - $FF). 3. Give XTAL1 a positive pulse. This loads the data high byte. G: Write Data High Byte 1. Set BS to "1". This selects high data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. (See Figure 51 for signal waveforms.) The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered: * * * The command needs only be loaded once when writing or reading multiple memory locations. Address high byte needs only be loaded before programming a new 256-word page in the Flash. Skip writing the data value $FF; that is, the contents of the entire Flash and EEPROM after a Chip Erase. These considerations also apply to EEPROM programming and Flash, EEPROM and signature byte reading. 65 0839G-08/01 Figure 50. Programming the Flash DATA $10 ADDR. HIGH ADDR. LOW DATA LOW XA1 XA0 BS XTAL1 WR RDY/BSY RESET OE 12V Figure 51. Programming the Flash (Continued) DATA DATA HIGH XA1 XA0 BS XTAL1 WR RDY/BSY RESET OE +12V Reading the Flash The algorithm for reading the Flash memory is as follows (refer to "Programming the Flash" for details on command and address loading): 1. A: Load Command "0000 0010". 2. B: Load Address High Byte ($00 - $03). 3. C: Load Address Low Byte ($00 - $FF). 4. Set OE to "0", and BS to "0". The Flash word low byte can now be read at DATA. 5. Set BS to "1". The Flash word high byte can now be read from DATA. 6. Set OE to "1". 66 AT90S2313 0839G-08/01 AT90S2313 Programming the EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to "Programming the Flash" for details on command, address and data loading): 1. A: Load Command "0001 0001". 2. C: Load Address Low Byte ($00 - $7F). 3. D: Load Data Low Byte ($00 - $FF). 4. E: Write Data Low Byte. Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to "Programming the Flash" for details on command and address loading): 1. A: Load Command "0000 0011". 2. C: Load Address Low Byte ($00 - $7F). 3. Set OE to "0", and BS to "0". The EEPROM data byte can now be read at DATA. 4. Set OE to "1". Programming the Fuse Bits The algorithm for programming the Fuse bits is as follows (refer to "Programming the Flash" for details on command and data loading): 1. A: Load Command "0100 0000". 2. D: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. Bit 5 = SPIEN Fuse bit. Bit 0 = FSTRT Fuse bit. Bit 7-6,4-1 = "1". These bits are reserved and should be left unprogrammed ("1"). 3. Give WR a tWLWH_PFB wide negative pulse to execute the programming; tWLWH_PFB is found in Table 26. Programming the Fuse bits does not generate any activity on the RDY/BSY pin. Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to "Programming the Flash" on page 64 for details on command and data loading): 1. A: Load Command "0010 0000". 2. D: Load Data Low Byte. Bit n = "0" programs the Lock bit. Bit 2 = Lock Bit2 Bit 1 = Lock Bit1 Bit 7-3,0 = "1". These bits are reserved and should be left unprogrammed ("1"). 3. E: Write Data Low Byte. The Lock bits can only be cleared by executing Chip Erase. Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to "Programming the Flash" on page 64 for details on command loading): 1. A: Load Command "0000 0100". 2. Set OE to "0", and BS to "1". The status of the Fuse and Lock bits can now be read at DATA ("0" means programmed). Bit 7 = Lock Bit1 Bit 6 = Lock Bit2 Bit 5 = SPIEN Fuse bit Bit 0 = FSTRT Fuse bit 3. Set OE to "1". Observe that BS needs to be set to "1". 67 0839G-08/01 Reading the Signature Bytes The algorithm for reading the signature bytes is as follows (refer to "Programming the Flash" on page 64 for details on command and address loading): 1. A: Load Command "0000 1000". 2. C: Load Address Low Byte ($00 - $02). Set OE to "0", and BS to "0". The selected signature byte can now be read at DATA. 3. Set OE to "1". Parallel Programming Characteristics Figure 52. Parallel Programming Timing tXLWL XTAL1 tDVXH Data & Contol (DATA, XA0/1, BS) WR RDY/BSY tWLRH tOLDV tRHBX tXHXL tXLDX tBVWL tWHRL DATA Table 26. Parallel Programming Characteristics, TA = 25C 10%, VCC = 5V 10% Symbol VPP IPP tDVXH tXHXL tXLDX tXLWL tBVWL tRHBX tWLWH tWHRL tWLRH tXLOL tOLDV tOHDZ tWLWH_CE tWLWH_PFB Notes: Parameter Programming Enable Voltage Programming Enable Current Data and Control Setup before XTAL1 High XTAL1 Pulse Width High Data and Control Hold after XTAL1 Low XTAL1 Low to WR Low BS Valid to WR Low BS Hold after RDY/BSY High WR Pulse Width Low(1) WR High to RDY/BSY Low(2) WR Low to RDY/BSY High XTAL1 Low to OE Low OE Low to DATA Valid OE High to DATA Tri-stated WR Pulse Width Low for Chip Erase WR Pulse Width Low for Programming the Fuse Bits 5.0 1.0 10.0 1.5 (2) Min 11.5 Typ Max 12.5 250.0 Units V A ns ns ns ns ns ns ns 67.0 67.0 67.0 67.0 67.0 67.0 67.0 20.0 0.5 67.0 20.0 20.0 15.0 1.8 0.7 0.9 ns ms ns ns ns ms ms 1. Use tWLWH_CE for chip erase and tWLWH_PFB for programming the Fuse bits. 2. If tWLWH is held longer than tWLRH, no RDY/BSY pulse will be seen. 68 AT90S2313 0839G-08/01 Read OE tXLOL tOHDZ Write tWLWH AT90S2313 Serial Downloading Both the program and data memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). See Figure 53. After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase instructions can be executed. Figure 53. Serial Programming and Verify )6'5 !! 2.7 - 6.0V VCC PB7 PB6 PB5 SCK MISO MOSI GND RESET CLOCK INPUT XTAL1 GND For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first execute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the program and EEPROM arrays into $FF. The program and EEPROM memory arrays have separate address spaces: $0000 to $03FF for program Flash memory and $000 to $07F for EEPROM data memory. Either an external clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 XTAL1 clock cycle High: > 2 XTAL1 clock cycles Serial Programming Algorithm When writing serial data to the AT90S2313, data is clocked on the rising edge of SCK. When reading data from the AT90S2313, data is clocked on the falling edge of SCK. See Figure 54, Figure and Table 29 for timing details. To program and verify the AT90S2313 in the Serial Programming Mode, the following sequence is recommended (See 4-byte instruction formats in Table 28): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". If a crystal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two XTAL1 cycles duration after SCK has been set to "0". 69 0839G-08/01 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to the MOSI (PB5) pin. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the second byte ($53) will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is no functional device connected. 4. If a Chip Erase is performed (must be done to erase the Flash), wait tWD_ERASE after the instruction, give RESET a positive pulse, and start over from step 2. See Table 30 for tWD_ERASE value. 5. The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. Use Data Polling to detect when the next byte in the Flash or EEPROM can be written. If polling is not used, wait tWD_PROG before transmitting the next instruction. See Table 31 for tWD_PROG value. In an erased device, no $FFs in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction that returns the content at the selected address at the serial output MISO (PB6) pin. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set XTAL1 to "0" (if a crystal is not used). Set RESET to "1". Turn VCC power off. Data Polling EEPROM When a byte is being programmed into the EEPROM, reading the address location being programmed will give the value P1 until the auto-erase is finished, and then the value P2. See Table 27 for P1 and P2 values. At the time the device is ready for a new EEPROM byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the values P1 and P2, so when programming these values, the user will have to wait for at least the prescribed time tWD_PROG before programming the next byte. See Table 30 for tWD_PROG value. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. This does not apply if the EEPROM is reprogrammed without first chip-erasing the device. Table 27. Read Back Value during EEPROM Polling Part AT90S2313 P1 $80 P2 $7F Data Polling Flash When a byte is being programmed into the Flash, reading the address location being programmed will give the value $7F. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $7F, so when programming this value, the user will have to wait for at least tWD_PROG before programming the next byte. As a chiperased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. 70 AT90S2313 0839G-08/01 AT90S2313 Figure 54. Serial Programming Waveforms Table 28. Serial Programming Instruction Set Instruction Format Instruction Programming Enable Chip Erase Byte 1 1010 1100 1010 1100 0010 H000 Read Program Memory 0100 H000 Write Program Memory Read EEPROM Memory Write EEPROM Memory Write Lock Bits 1010 0000 1100 0000 1010 1100 xxxx xxxx xxxx xxxx 111x x21x xxxx xxxx xbbb bbbb xbbb bbbb xxxx xxxx xxxx xxbb oooo oooo iiii iiii xxxx xxxx oooo oooo xxxx xxaa bbbb bbbb iiii iiii Byte 2 0101 0011 100x xxxx xxxx xxaa Byte 3 xxxx xxxx xxxx xxxx bbbb bbbb Byte4 xxxx xxxx xxxx xxxx oooo oooo Operation Enable serial programming while RESET is low. Chip erase Flash and EEPROM memory arrays. Read H (high or low) data o from program memory at word address a:b. Write H (high or low) data i to program memory at word address a:b. Read data o from EEPROM memory at address b. Write data i to EEPROM memory at address b. Write Lock bits. Set bits 1,2 = "0" to program Lock bits. Read signature byte o at address b.(1) Read Signature Bytes 0011 0000 Note: a = address high bits b = address low bits H = 0 - Low byte, 1 - High Byte o = data out i = data in x = don't care 1 = Lock bit 1 2 = Lock bit 2 Note: 1. The signature bytes are not readable in lock mode 3, i.e. both Lock bits programmed. 71 0839G-08/01 Serial Programming Characteristics Figure 55. Serial Programming Timing MOSI tOVSH SCK MISO tSLIV tSHSL tSHOX tSLSH Table 29. Serial Programming Characteristics, TA = -40C to 85C, VCC = 2.7 - 6.0V (unless otherwise noted) Symbol 1/tCLCL tCLCL 1/tCLCL tCLCL tSHSL tSLSH tOVSH tSHOX tSLIV Parameter Oscillator Frequency (VCC = 2.7 - 6.0V) Oscillator Period (VCC = 2.7 - 6.0V) Oscillator Frequency (VCC = 4.0 - 6.0V) Oscillator Period (VCC = 4.0 - 6.0V) SCK Pulse Width High SCK Pulse Width Low MOSI Setup to SCK High MOSI Hold after SCK High SCK Low to MISO Valid Min 0 250.0 0 100.0 2.0 tCLCL 2.0 tCLCL tCLCL 2.0 tCLCL 10.0 16.0 32.0 10.0 Typ Max 4.0 Units MHz ns MHz ns ns ns ns ns ns Table 30. Minimum Wait Delay after the Chip Erase Instruction Symbol tWD_ERASE 3.2V 18 ms 3.6V 14 ms 4.0V 12 ms 5.0V 8 ms Table 31. Minimum Wait Delay after Writing a Flash or EEPROM Location Symbol tWD_PROG 3.2V 9 ms 3.6V 7 ms 4.0V 6 ms 5.0V 4 ms 72 AT90S2313 0839G-08/01 AT90S2313 Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin Except RESET with Respect to Ground ...............................-1.0V to VCC+0.5V Voltage on RESET with Respect to Ground ....-1.0V to +13.0V Maximum Operating Voltage ............................................ 6.6V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins ................................ 200.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = -40C to 85C, VCC = 2.7V to 6.0V (unless otherwise noted) Symbol VIL VIL1 VIH VIH1 VIH2 VOL VOH IIL IIH RRST RI/O ICC ICC VACIO IACLK tACPD Parameter Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Input High Voltage Output Low Voltage(3) (Ports B, D) Output High Voltage(4) (Ports B, D) Input Leakage Current I/O pin Input Leakage Current I/O pin Reset Pull-up Resistor I/O Pin Pull-up Resistor Power Supply Current Active Mode, VCC = 3V, 4 MHz Idle Mode VCC = 3V, 4 MHz WDT enabled, VCC = 3V WDT disabled, VCC = 3V VCC = 5V Vin = VCC /2 VCC = 5V Vin = VCC/2 VCC = 2.7V VCC = 4.0V -50.0 750.0 500.0 9.0 <1.0 Condition (Except XTAL1) (XTAL1) (Except XTAL1, RESET) (XTAL1) (RESET) IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V IOH = -3 mA, VCC = 5V IOH = -1.5 mA, VCC = 3V VCC = 6V, pin low (absolute value) VCC = 6V, pin high (absolute value) 100.0 35.0 4.3 2.3 1.5 980.0 500.0 120.0 3.0 1.0 15.0 2.0 40.0 50.0 Min -0.5 -0.5 0.6 VCC 0.7 VCC (2) (2) (2) Typ Max 0.3 VCC (1) Units V V V V V V V V V A nA k k mA mA A A mV nA ns 0.3 VCC(1) VCC + 0.5 VCC + 0.5 VCC + 0.5 0.6 0.5 0.85 VCC Power-down Mode(5) Analog Comparator Input Offset Voltage Analog Comparator Input Leakage Current Analog Comparator Propagation Delay 73 0839G-08/01 Notes: 1. "Max" means the highest value where the pin is guaranteed to be read as low. 2. "Min" means the lowest value where the pin is guaranteed to be read as high. 3. Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOL, for all ports, should not exceed 200 mA 2] The sum of all IIOL, for port D0 - D5 and XTAL2 should not exceed 100 mA. 3] The sum of all IOL, for ports B0 - B7 and D6 should not exceed 100 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (3 mA at VCC = 5V, 1.5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOH, for all ports, should not exceed 200 mA 2] The sum of all IOH, for port D0 - D5 and XTAL2 should not exceed 100 mA. 3] The sum of all IOH, for ports B0 - B7 and D6 should not exceed 100 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum VCC for power-down is 2V. External Clock Drive Waveforms Figure 56. External Clock VIH1 VIL1 External Clock Drive VCC = 2.7V to 6.0V Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time Min 0 250.0 100.0 100.0 1.6 1.6 Max 4 VCC = 4.0V to 6.0V Min 0 100.0 40.0 40.0 0.5 0.5 Max 10.0 Units MHz ns ns ns s s 74 AT90S2313 0839G-08/01 AT90S2313 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. The power consumption in Power-Down Mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL * V CC * f where C L = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down Mode with Watchdog timer enabled and Power-down Mode with Watchdog timer disabled represents the differential current drawn by the Watchdog timer. Figure 57. Active Supply Current vs. Frequency ACTIVE SUPPLY CURRENT vs. FREQUENCY TA= 25C # Vcc= 6V Vcc= 5.5V Vcc= 5V I cc(mA) # Vcc= 4.5V Vcc= 4V Vcc= 3.6V Vcc= 3.3V Vcc= 3.0V Vcc= 2.7V # ! " # $ % & ' ! " # Frequency (MHz) 75 0839G-08/01 Figure 58. Active Supply Current vs. VCC ACTIVE SUPPLY CURRENT vs. Vcc FREQUENCY = 4 MHz 12 10 TA = 25C TA = 85C 8 I cc(mA) 6 4 2 0 2 2.5 3 3.5 4 Vcc(V) 4.5 5 5.5 6 Figure 59. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY TA= 25C 8 7 6 5 I cc(mA) Vcc= 6V Vcc= 5.5V Vcc= 5V Vcc= 4.5V Vcc= 4V Vcc= 3.6V Vcc= 3.3V Vcc= 3.0V Vcc= 2.7V 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Frequency (MHz) 76 AT90S2313 0839G-08/01 AT90S2313 Figure 60. Idle Supply Current vs. VCC IDLE SUPPLY CURRENT vs. Vcc FREQUENCY = 4 MHz 3.5 3 TA = 25C 2.5 TA = 85C I cc(mA) 2 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 61. Power-down Supply Current vs. VCC POWER DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER DISABLED 2 1.8 1.6 1.4 I cc() TA = 85C 1.2 1 0.8 0.6 0.4 0.2 0 2 2.5 3 3.5 Vcc(V) TA = 45C TA = 25C TA = 70C 4 4.5 5 5.5 6 77 0839G-08/01 Figure 62. Power-down Supply Current vs. VCC POWER DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER ENABLED 160 140 120 TA = 85C I cc() TA = 25C 100 80 60 40 20 0 2 2.5 3 3.5 4 Vcc(V) 4.5 5 5.5 6 Figure 63. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. Vcc 0.9 0.8 0.7 0.6 TA = 85C I cc(mA) TA = 25C 0.5 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 Vcc(V) 4 4.5 5 5.5 6 78 AT90S2313 0839G-08/01 AT90S2313 Note: Analog Comparator offset voltage is measured as absolute offset. Figure 64. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 5V 18 16 TA = 25C 14 Offset Voltage (mV) 12 TA = 85C 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) Figure 65. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 2.7V 10 TA = 25C 8 Offset Voltage (mV) 6 TA = 85C 4 2 0 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) 79 0839G-08/01 Figure 66. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT VCC = 6V TA = 25C 60 50 40 (nA) I ACLK 30 20 10 0 -10 0 0.5 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 5.5 6 6.5 7 Figure 67. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. Vcc 1600 TA = 25C 1400 TA = 85C 1200 F RC (KHz) 1000 800 600 400 200 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc (V) 80 AT90S2313 0839G-08/01 AT90S2313 Note: Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 68. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 120 TA = 25C 100 TA = 85C 80 OP (A) I 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 69. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 30 TA = 25C 25 TA = 85C 20 OP (A) 15 I 10 5 0 0 0.5 1 1.5 2 2.5 3 VOP (V) 81 0839G-08/01 Figure 70. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 70 TA = 25C 60 TA = 85C 50 40 OL (mA) 30 I 20 10 0 0 0.5 1 1.5 2 2.5 3 VOL (V) Figure 71. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 20 TA = 25C 18 16 TA = 85C 14 12 OH (mA) 10 8 I 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOH (V) 82 AT90S2313 0839G-08/01 AT90S2313 Figure 72. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 25 TA = 25C 20 TA = 85C 15 OL (mA) 10 I 5 0 0 0.5 1 1.5 2 VOL (V) Figure 73. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 6 TA = 25C 5 TA = 85C 4 OH (mA) 3 I 2 1 0 0 0.5 1 1.5 2 2.5 3 VOH (V) 83 0839G-08/01 Figure 74. I/O Pin Input Threshold Voltage vs. VCC I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc TA = 25C 2.5 2 Threshold Voltage (V) 1.5 1 0.5 0 2.7 4.0 5.0 Vcc Figure 75. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. Vcc TA = 25C 0.18 0.16 0.14 Input hysteresis (V) 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 5.0 Vcc 84 AT90S2313 0839G-08/01 AT90S2313 Register Summary Address $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) ... $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) ... $00 ($20) Name SREG Reserved SPL Reserved GIMSK GIFR TIMSK TIFR Reserved Reserved MCUCR Reserved TCCR0 TCNT0 Reserved Reserved TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL Reserved Reserved Reserved Reserved ICR1H ICR1L Reserved Reserved WDTCR Reserved Reserved EEAR EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB Reserved Reserved Reserved PORTD DDRD PIND Reserved UDR USR UCR UBRR ACSR Reserved Reserved Bit 7 I SP7 INT1 INTF1 TOIE1 TOV1 Bit 6 T SP6 INT0 INTF0 OCIE1A OCF1A Bit 5 H SP5 - Bit 4 S SP4 - Bit 3 V SP3 TICIE1 ICF1 Bit 2 N SP2 - Bit 1 Z SP1 TOIE0 TOV0 Bit 0 C SP0 - Page page 17 page 18 page 23 page 23 page 24 page 24 - - SE - SM ISC11 ISC10 CS02 ISC01 CS01 ISC00 CS00 page 26 page 29 page 30 Timer/Counter0 (8 Bits) COM1A1 ICNC1 COM1A0 ICES1 . CTC1 CS12 Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Compare Register High Byte Timer/Counter1 - Compare Register Low Byte PWM11 CS11 PWM10 CS10 page 31 page 32 page 33 page 33 page 34 page 34 Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte page 35 page 35 - - - WDTOE WDE WDP2 WDP1 WDP0 page 38 - EEPROM Address Register EEPROM Data Register EEMWE EEWE EERE page 40 page 40 page 40 PORTB7 DDB7 PINB7 PORTB6 DDB6 PINB6 PORTB5 DDB5 PINB5 PORTB4 DDB4 PINB4 PORTB3 DDB3 PINB3 PORTB2 DDB2 PINB2 PORTB1 DDB1 PINB1 PORTB0 DDB0 PINB0 page 52 page 52 page 52 - PORTD6 DDD6 PIND6 PORTD5 DDD5 PIND5 PORTD4 DDD4 PIND4 PORTD3 DDD3 PIND3 PORTD2 DDD2 PIND2 PORTD1 DDD1 PIND1 PORTD0 DDD0 PIND0 page 58 page 58 page 58 page 46 page 46 page 47 page 49 page 50 RXC RXCIE ACD TXC TXCIE - UDRE UDRIE ACO UART I/O Data Register FE OR RXEN TXEN UART Baud Rate Register ACI ACIE CHR9 ACIC RXB8 ACIS1 TXB8 ACIS0 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical "1" to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a "1" back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. 85 0839G-08/01 Instruction Set Summary Mnemonic Operands Description Operation Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rdh:Rdl Rdh:Rdl - K Rd Rd - Rr - C Rd Rd - K - C Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z,N,V,C,H Z,N,V,C,H Z,N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None # Clocks 1 1 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2 1 1 1 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers ADIW Rdl, K Add Immediate to Word SUB Rd, Rr Subtract Two Registers SUBI Rd, K Subtract Constant from Register SBIW Rdl, K Subtract Immediate from Word SBC Rd, Rr Subtract with Carry Two Registers SBCI Rd, K Subtract with Carry Constant from Reg. AND Rd, Rr Logical AND Registers ANDI Rd, K Logical AND Register and Constant OR Rd, Rr Logical OR Registers ORI Rd, K Logical OR Register and Constant EOR Rd, Rr Exclusive OR Registers COM Rd One's Complement NEG Rd Two's Complement SBR Rd, K Set Bit(s) in Register CBR Rd, K Clear Bit(s) in Register INC Rd Increment DEC Rd Decrement TST Rd Test for Zero or Minus CLR Rd Clear Register SER Rd Set Register BRANCH INSTRUCTIONS RJMP k Relative Jump IJMP Indirect Jump to (Z) RCALL k Relative Subroutine Call ICALL Indirect Call to (Z) RET Subroutine Return RETI Interrupt Return CPSE Rd, Rr Compare, Skip if Equal CP Rd, Rr Compare CPC Rd, Rr Compare with Carry CPI Rd, K Compare Register with Immediate SBRC Rr, b Skip if Bit in Register Cleared SBRS Rr, b Skip if Bit in Register is Set SBIC P, b Skip if Bit in I/O Register Cleared SBIS P, b Skip if Bit in I/O Register is Set BRBS s, k Branch if Status Flag Set BRBC s, k Branch if Status Flag Cleared BREQ k Branch if Equal BRNE k Branch if Not Equal BRCS k Branch if Carry Set BRCC k Branch if Carry Cleared BRSH k Branch if Same or Higher BRLO k Branch if Lower BRMI k Branch if Minus BRPL k Branch if Plus BRGE k Branch if Greater or Equal, Signed BRLT k Branch if Less than Zero, Signed BRHS k Branch if Half-carry Flag Set BRHC k Branch if Half-carry Flag Cleared BRTS k Branch if T-Flag Set BRTC k Branch if T-Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled Rd - Rr Rd - Rr - C Rd - K if (Rr(b) = 0) PC PC + 2 or 3 if (Rr(b) = 1) PC PC + 2 or 3 if (P(b) = 0) PC PC + 2 or 3 if (R(b) = 1) PC PC + 2 or 3 if (SREG(s) = 1) then PC =PC + k + 1 if (SREG(s) = 0) then PC =PC + k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V = 0) then PC PC + k + 1 if (N V = 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if (I = 1) then PC PC + k + 1 if (I = 0) then PC PC + k + 1 86 AT90S2313 0839G-08/01 AT90S2313 Instruction Set Summary (Continued) Mnemonic Operands Description Move between Registers Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left through Carry Rotate Right through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit Load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Two's Complement Overflow Clear Two's Complement Overflow Set T in SREG Clear T in SREG Set Half-carry Flag in SREG Clear Half-carry Flag in SREG No Operation Sleep Watchdog Reset Operation Rd Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0) =C, Rd(n+1) Rd(n), C =Rd(7) Rd(7) =C, Rd(n) Rd(n+1), C =Rd(0) Rd(n) Rd(n+1), n = 0..6 Rd(3..0) =Rd(7..4), Rd(7..4) =Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 (see specific descr. for Sleep function) (see specific descr. for WDR/timer) Flags None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None # Clocks 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr LDI Rd, K LD Rd, X LD Rd, X+ LD Rd, -X LD Rd, Y LD Rd, Y+ LD Rd, -Y LDD Rd, Y+q LD Rd, Z LD Rd, Z+ LD Rd, -Z LDD Rd, Z+q LDS Rd, k ST X, Rr ST X+, Rr ST -X, Rr ST Y, Rr ST Y+, Rr ST -Y, Rr STD Y+q, Rr ST Z, Rr ST Z+, Rr ST -Z, Rr STD Z+q, Rr STS k, Rr LPM IN Rd, P OUT P, Rr PUSH Rr POP Rd BIT AND BIT-TEST INSTRUCTIONS SBI P, b CBI P, b LSL Rd LSR Rd ROL Rd ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR 87 0839G-08/01 Ordering Information Speed (MHz) 4 Power Supply 2.7 - 6.0V Ordering Code AT90S2313-4PC AT90S2313-4SC AT90S2313-4PI AT90S2313-4SI 10 4.0 - 6.0V AT90S2313-10PC AT90S2313-10SC AT90S2313-10PI AT90S2313-10SI Package 20P3 20S 20P3 20S 20P3 20S 20P3 20S Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Package Type 20P3 20S 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 88 AT90S2313 0839G-08/01 AT90S2313 Packaging Information 20P3, 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 BA 1.060(26.9) .980(24.9) 0.020 (0.508) 0.013 (0.330) 20S, 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters) PIN 1 .280(7.11) .240(6.10) PIN 1 0.299 (7.60) 0.420 (10.7) 0.291 (7.39) 0.393 (9.98) .900(22.86) REF .210(5.33) MAX SEATING PLANE .150(3.81) .115(2.92) .110(2.79) .090(2.29) .070(1.78) .045(1.13) .090(2.29) MAX .005(.127) MIN .050 (1.27) BSC .015(.381) MIN .022(.559) .014(.356) 0.513 (13.0) 0.497 (12.6) 0.105 (2.67) 0.092 (2.34) 0.012 (0.305) 0.003 (0.076) .325(8.26) .300(7.62) .014(.356) .008(.203) 0 REF 15 .430(10.92) MAX 0.035 (0.889) 0.015 (0.381) 0 REF 8 0.013 (0.330) 0.009 (0.229) 89 0839G-08/01 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Atmel Product Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-7658-3000 FAX (33) 4-7658-3480 Theresienstrasse 2 POB 3535 D-74025 Heilbronn, Germany TEL (49) 71 31 67 25 94 FAX (49) 71 31 67 24 23 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 0 2 40 18 18 18 FAX (33) 0 2 40 18 19 60 Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Scottish Enterprise Technology Park East Kilbride, Scotland G75 0QR TEL (44) 1355-357-000 FAX (44) 1355-242-743 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Atmel Grenoble Atmel Heilbronn Asia Atmel Nantes Japan Atmel Rousset Atmel Smart Card ICs Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 literature@atmel.com Web Site BBS http://www.atmel.com 1-(408) 436-4309 (c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Marks bearing (R) and/or TM are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. 0839G-08/01/xM |
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